(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming both NLDD and N+ or PLDD and P+ regions in one implantation in the fabrication of integrated circuits.
(2) Description of the Prior Art
In scaling down semiconductor devices, thinner gate oxide and higher doped channels are required for short channel devices. These measures increase the electric field near the drain regions. Charge carriers are accelerated by the electric field and become "hot" carriers. These hot carriers can overcome the oxide barrier and inject into the gate or become trapped in the gate oxide degrading device performance. This is the so-called hot carrier effect and is discussed, for example, in ULSI Technology, by C. Y. Chang and S. M. Sze, McGraw-Hill Co, Inc, New York, N.Y., c. 1996, p. 480. The lightly doped drain (LDD) reduces this drain field, thereby alleviating the hot carrier effect. However, the conventional LDD process takes much cycle time and strenuous steps. The drain is conventionally formed by two implants.
U.S. Pat. No. 4,771,014 to Liou et al teaches a LDD CMOS process using unmasked blanket implants. U.S. Pat. No. 5,858,847 to Zhou et al forms the source/drain first using a photoresist block, and then implanting the LDD. U.S. Pat. No. 5,141,891 to Arima et al discloses a polysilicon source drain (PSD) and a LDD structure. U.S. Pat. No. 5,780,903 to Tsai et al forms an LDD using a photoresist ion implant mask and two implantations.